IWOCL 2025, 13th International Workshop on OpenCL and SYCL, 7-11 April 2025, Heidelberg, Germany
Over the past few years, RISC-V has emerged as an open and extensible architecture with flexible vector extensions (RVV) for scaling computationally-intensive workloads. On the software side, SYCL has emerged as a standardized, cross-architecture programming
model that can provide performance portability across several accelerators. In this work, we describe our efforts to bring these two standards together by extending the integration of CVA6 RISC-V core with the ARA2 RVV implementation to enable SYCL kernel
offload via the oneAPI Construction Kit.
Type:
Poster / Demo
City:
Heidelberg
Date:
2025-04-07
Department:
Data Science
Eurecom Ref:
8201
Copyright:
© ACM, 2025. This is the author's version of the work. It is posted here by permission of ACM for your personal use. Not for redistribution. The definitive version was published in IWOCL 2025, 13th International Workshop on OpenCL and SYCL, 7-11 April 2025, Heidelberg, Germany https://doi.org/10.1145/3731125.3731136
